USRP Hardware Driver and USRP Manual  Version: 3.12.0.0-0-unknown
UHD and USRP Manual
constants.hpp
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1 //
2 // Copyright 2014 Ettus Research LLC
3 // Copyright 2018 Ettus Research, a National Instruments Company
4 //
5 // SPDX-License-Identifier: GPL-3.0-or-later
6 //
7 
8 #ifndef INCLUDED_LIBUHD_RFNOC_CONSTANTS_HPP
9 #define INCLUDED_LIBUHD_RFNOC_CONSTANTS_HPP
10 
11 #include <uhd/types/dict.hpp>
12 #include <boost/assign/list_of.hpp>
13 #include <stdint.h>
14 #include <string>
15 
16 namespace uhd {
17  namespace rfnoc {
18 
19 // All these configure the XML reader
21 static const std::string XML_DEFAULT_PATH = "share/uhd/rfnoc";
23 static const std::string XML_PATH_ENV = "UHD_RFNOC_DIR";
24 
26 static const std::string DEFAULT_BLOCK_NAME = "Block";
27 static const uint64_t DEFAULT_NOC_ID = 0xFFFFFFFFFFFFFFFF;
28 static const size_t NOC_SHELL_COMPAT_MAJOR = 2;
29 static const size_t NOC_SHELL_COMPAT_MINOR = 0;
30 
31 static const size_t MAX_PACKET_SIZE = 8000; // bytes
32 static const size_t DEFAULT_PACKET_SIZE = 1456; // bytes
33 
34 // One line in FPGA is 64 Bits
35 static const size_t BYTES_PER_LINE = 8;
36 
38 static const size_t DEFAULT_FC_XBAR_PKTS_PER_ACK = 2;
40 static const size_t DEFAULT_FC_RX_RESPONSE_FREQ = 64; // ACKs per flow control window
42 static const size_t DEFAULT_FC_TX_RESPONSE_FREQ = 8; // ACKs per flow control window
44 // Why not 100% full? Because we need to have some headroom to account for the inaccuracy
45 // when computing the window size. We compute the flow control window based on the frame
46 // size but the buffer can have overhead due to things like UDP headers, page alignment,
47 // housekeeping info, etc. This number has to be transport agnostic so 20% of headroom is safe.
48 static const double DEFAULT_FC_RX_SW_BUFF_FULL_FACTOR = 0.80;
49 
50 // Common settings registers.
51 static const uint32_t SR_FLOW_CTRL_CYCS_PER_ACK = 0;
52 static const uint32_t SR_FLOW_CTRL_PKTS_PER_ACK = 1;
53 static const uint32_t SR_FLOW_CTRL_WINDOW_SIZE = 2;
54 static const uint32_t SR_FLOW_CTRL_WINDOW_EN = 3;
55 static const uint32_t SR_ERROR_POLICY = 4;
56 static const uint32_t SR_BLOCK_SID = 5; // TODO rename to SRC_SID
57 static const uint32_t SR_NEXT_DST_SID = 6;
58 static const uint32_t SR_RESP_IN_DST_SID = 7;
59 static const uint32_t SR_RESP_OUT_DST_SID = 8;
60 
61 static const uint32_t SR_READBACK_ADDR = 124;
62 static const uint32_t SR_READBACK = 127;
63 
64 static const uint32_t SR_CLEAR_RX_FC = 125;
65 static const uint32_t SR_CLEAR_TX_FC = 126;
66 
71  SR_READBACK_REG_FIFOSIZE = 2, // fifo size
76 };
77 
78 // AXI stream configuration bus (output master bus of axi wrapper) registers
79 static const uint32_t AXI_WRAPPER_BASE = 128;
80 static const uint32_t AXIS_CONFIG_BUS = AXI_WRAPPER_BASE+1; // tdata with tvalid asserted
81 static const uint32_t AXIS_CONFIG_BUS_TLAST = AXI_WRAPPER_BASE+2; // tdata with tvalid & tlast asserted
82 
83 static const size_t CMD_FIFO_SIZE = 128; // Lines == multiples of 8 bytes
84 
85 // Named settings registers
86 static const uhd::dict<std::string, uint32_t> DEFAULT_NAMED_SR = boost::assign::map_list_of
87  ("AXIS_CONFIG_BUS", AXIS_CONFIG_BUS)
88  ("AXIS_CONFIG_BUS_TLAST", AXIS_CONFIG_BUS_TLAST)
89 ;
90 
91 // Block ports
92 static const size_t ANY_PORT = size_t(~0);
93 static const size_t MAX_NUM_PORTS = 16;
94 
95 // Regular expressions
96 static const std::string VALID_BLOCKNAME_REGEX = "[A-Za-z][A-Za-z0-9]*";
97 static const std::string VALID_BLOCKID_REGEX = "(?:(\\d+)(?:/))?([A-Za-z][A-Za-z0-9]*)(?:(?:_)(\\d\\d?))?";
98 
99 }} /* namespace uhd::rfnoc */
100 
101 #endif /* INCLUDED_LIBUHD_RFNOC_CONSTANTS_HPP */
102 // vim: sw=4 et:
Definition: constants.hpp:70
Definition: constants.hpp:69
Definition: constants.hpp:71
Definition: dict.hpp:20
settingsbus_reg_t
Settings register readback.
Definition: constants.hpp:68
Definition: build_info.hpp:14
Definition: constants.hpp:74
Definition: constants.hpp:75
Definition: constants.hpp:73
Definition: constants.hpp:72