ztex_inouttraffic Project Status (08/18/2018 - 10:47:51)
Project File: fpga-sha256crypt.xise Parser Errors: No Errors
Module Name: ztex_inouttraffic Implementation State: Programming File Generated
Target Device: xc6slx150-3csg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3199 Warnings (3199 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: sha256crypt
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
1792  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 72,023 184,304 39%  
    Number used as Flip Flops 66,798      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 5,225      
Number of Slice LUTs 62,888 92,152 68%  
    Number used as logic 49,331 92,152 53%  
        Number using O6 output only 27,323      
        Number using O5 output only 1,154      
        Number using O5 and O6 20,854      
        Number used as ROM 0      
    Number used as Memory 4,415 21,680 20%  
        Number used as Dual Port RAM 3,999      
            Number using O6 output only 1,238      
            Number using O5 output only 53      
            Number using O5 and O6 2,708      
        Number used as Single Port RAM 165      
            Number using O6 output only 129      
            Number using O5 output only 10      
            Number using O5 and O6 26      
        Number used as Shift Register 251      
            Number using O6 output only 126      
            Number using O5 output only 0      
            Number using O5 and O6 125      
    Number used exclusively as route-thrus 9,142      
        Number with same-slice register load 9,034      
        Number with same-slice carry load 108      
        Number with other load 0      
Number of occupied Slices 20,439 23,038 88%  
Number of MUXCYs used 17,932 46,076 38%  
Number of LUT Flip Flop pairs used 67,233      
    Number with an unused Flip Flop 13,365 67,233 19%  
    Number with an unused LUT 4,345 67,233 6%  
    Number of fully used LUT-FF pairs 49,523 67,233 73%  
    Number of unique control sets 3,080      
    Number of slice register sites lost
        to control set restrictions
7,824 184,304 4%  
Number of bonded IOBs 44 338 13%  
    Number of LOCed IOBs 44 44 100%  
    IOB Flip Flops 62      
Number of RAMB16BWERs 9 268 3%  
Number of RAMB8BWERs 326 536 60%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 4 16 25%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 2 12 16%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 1      
Number of ILOGIC2/ISERDES2s 20 586 3%  
    Number used as ILOGIC2s 20      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 22 586 3%  
    Number used as OLOGIC2s 22      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 6 16%  
    Number of LOCed PLL_ADVs 1 1 100%  
Number of PMVs 0 1 0%  
Number of STARTUPs 1 1 100%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.90      
 
Performance Summary [-]
Final Timing Score: 1792 (Setup: 1792, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentбс 18. рту 09:45:27 20180170 Warnings (170 new)42 Infos (42 new)
Translation ReportCurrentбс 18. рту 09:47:11 2018000
Map ReportCurrentбс 18. рту 10:14:14 201801202 Warnings (1202 new)545 Infos (545 new)
Place and Route ReportCurrentбс 18. рту 10:31:21 20180914 Warnings (914 new)2 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentбс 18. рту 10:47:43 201801 Warning (1 new)3 Infos (3 new)
Bitgen ReportCurrentбс 18. рту 10:39:54 20180912 Warnings (912 new)1 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateбс 18. рту 07:29:45 2018
WebTalk Log FileCurrentбс 18. рту 10:40:02 2018

Date Generated: 08/18/2018 - 10:47:51